Silicon double doped with p and as or b and as

ABSTRACT

A silicon semiconductor device double doped with phosphorus and arsenic or boron and arsenic, the arsenic being present in an amount 3 to 40 percent of the other dopant and preventing lattice collapse with heavy doping concentrations.

United States Paten Nakamura et al.

SILICON DOUBLE DOPED WITH P AND AS OR B AND AS [51] Int. Cl. Hll 3/14Inventors: Masakatsu Nakamura; Toshio [58] Fleld of Search 317/235 AQYonezawa; Taketoshi Kato, all of Yokohama; Masaharu Watanabe, [56]References Cited K i; Minor Akalsuka, UNITED STATES PATENTS Yokohama ofJapan 3,485,684 l2/l969 Mann et al 317/235 AQ Assignee:

Filed: June Appl. No.: 263,994

Related Application Data Tokyo Shibaura Electric Co., Ltd.,Kawasaki-shi, Japan Primary Examiner-John W. Huckert AssistantExaminer-William D. Larkins Division of Ser. No. 78,8l9, Oct. 7, 1970.

Foreign Application Priority Data Feb. 7, 1970 Japan 45-l0376 phosphorusand arsenic or boron and arsenic the ab senic being present in an amount3 to 40 percent of Mar. I3, 1970 Japan 45-20826 the other dopam andpreventing lattice co lapse with Mar. 28, i970 Japan 45-25627 heavy p gconcentrations. 4

US. Cl. 317/234 R, 148/l90, 317/235 AB.

[ 5 7 ABSTRACT 10 Claims, Drawing Figures Eas 1 I 5 7 H I I Toa- 1 r I,11 11 u O IO 20 3O 4O 8O ATO RATIOOF A MP (96) .3 May 21, 1974 3l7/235AQ. 317/235 AS Edel, Stress Relief by Counterdoping", IBM Tech. Discl.Bull, Vol. 13, No. 3, Aug. 1970, p. 632.

A silicon semiconductor device double doped with FIG. 1A FIG.1B

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2 4 DIFFUSION DEPTH (J 9 h EoEoFS zoifizwozoo f| This is a division ofapplication Ser. No. 78,819, filed Oct. 7, 1970.

This invention relates to semiconductor devices including regionscontaining impurities at high concentrations and a method ofmanufacturing such semiconductor devices.

' A prior art NPN-type semiconductor device or a high frequencysemiconductor device, for example, comprises an N-type conductivitysilicon substrate of collector region, a P-type conductivity base regionformed by diffusing a P-type conductivity impurity into one surface atthe substrate and forming a junction together with the substrate, and anN -type conductivity emitter region formed by diffusing into the baseregion an N- type impurity such as phosphorus oxychloride (POC1 While,it is desired that the emitter region contains the impurity at highconcentrations, diffusion of a large quantity of the impurity forobtaining high concentrations results in such lattice defects asdislocations and segregations. The same problem arises in integratedcircuits including many semiconductor elements.

Prior diodes, for example, a P NN -type diode comprises an N-typeconductivity silicon substrate, an N"- type conductivity region formedby diffusion at a high concentration, an N-type conductivity impurityinto one surface of the substrate, and a P -type conductivity regionformed by diffusing a P-type conductivity impurity into the othersurface of the substrate. In such a diode it is necessary to diffuse theP region at ahigh concentration, using boron nitride (BN), so thatlattice defects are generally present in the P region. Further in aswitching diode, gold is diffused in the surface of the substrate on theside in which the P -type region has been formed to obtain the diode ofthe type described above, to decrease the life time whereby to provide aswitching time of 1.5 microseconds for example (at I mA, V 10 V).

The silicon controlled rectifier element (hereinafter abbreviated asSCR) generally comprises an N-type conductivity silicon substrate, aP-type conductivity anode region and a gate region formed by diffusing aP-type conductivity impurity into opposite surfaces of the substrate andan N -type conductivity cathode region formed by diffusing into the gateregion an N-type conductivity impurity such as phosphorus oxychloride(POCI When forming the N -type conductivity cathode region having anincreased concentration of the impurity, the number of the latticedefects is also increased to impair the characteristics of the SCR.Thus, in order to decrease the number of lattice defects it is necessaryto decrease the concentration of the impurity.

, in a circuit element of the NPN construction such as a semiconductordevice or an integrated circuit device, in forming the N -typeconductivity region acting as the emitter region, it is important toincrease the impurity concentration of that region in order to decreasethe noise figure, to improve electrical characteristics and thestability of the circuit element. This is also true in semiconductordevices for high frequency applications. More particularly, when formingdiffused regions containing the impurity of the above described type ata high concentration, strains are formed due to compression stresscaused by the difference between the tetrahedral radius of silicon atomsof the substrate and the tetrahedral radius of the diffused impurity,such as phosphorus, boron, etc. Moreover, as the concentration of theatoms of the diffused impurity is increased, the impurity tends toprecipitate to create strains.

These strains cause lattice defects. For this reason, it

has been impossible to increase the impurity concentration.

Further, in such circuit elements as high frequency semiconductordevices and integrated circuit devices it is necessary to decrease thebase width of such circuit elements, or to decrease the time requiredfor the carriers to pass through thebase. In the manufacture of a highfrequency semiconductor device, a base region of a given width is formedon one surface of a substrate and then an emitter region is formed inthe base region by diffusing an impurity. In such a case, there occurs aphenomenon known as the emitter dip effect (EDE) according to which thewidth of the base region tends to increase. For this reason, it has beendifficult to obtain high frequency semiconductor devices having baseregions of sufficiently small width.

Further, in switching diodes of the PNN or P NN construction, as theswitching'time is inversely proportional to the concentration of thegold diffused, in order to provide constant switching time it isnecessary to strictly control the concentration of the gold near the PNjunction within limits of i 5 percent. However, when phosphorus isdifi'used by utilizing aforementioned phosphorus oxychloride (POCl thephosphorus atoms are diffused into the silicon substrate up to the solidsolution limit of the phosphor atoms with the result that a number ofsegregations and dislocations are formed and the gold deposits in theselattice defects to decrease the number of gold atomsnear the PNjunction. For this reason, it has been difiicult to obtain the desiredgold concentration and to produce diodes of constant switching time.

Also in silicon controlled rectifiers it is important to avoid formationof lattice defects in order to prevent decrease in the forward voltagedrop and deterioration of various characteristics due to heathysteresis. With the above described construction it has been difficultto solve these problems.

It is an object of this invention to provide an improved semiconductordevice including a semiconductor substrate formed with a region dopedwith an impurity at a high concentration without forming segregations orlattice defects in the substrate.

Another object of this invention is to provide a semiconductor deviceformed with a base region of narrow width without the emitter dipeffect.

Still another object of this invention is to provide a novel method ofmanufacturing a semiconductor device capable of forming a region of thedesired impurity concentration without forming segregations ordislocations in the semiconductor substrate.

Yet another object of this invention is to provide a new and improvedmethod of manufacturing a semiconductor device capable of forming anemitter region in the base region without accompanying undesirableemitter dip effect.

According to this invention there is provided a semiconductor deviceincluding a region containing impurities at high concentrations whereinthe impurities comprise arsenic and at least one impurity other thanarsenic and wherein the number of atoms of arsenic is smaller than thatof the other impurity at the surface of the region. As a consequencethere is no fear of forming segregations or lattice defects in theregion containing impurities, and moreover above described. emitter dipeffect can be avoided where the impurity region is formed to act as theemitter region of a transistor.

In order to more efficien'tly prevent the formation of segregations andlattice defects it is advantageous to use a (111) face as the mainsurface of the substrate in which the impurity region is to be formed orto form the substrate to have dislocation free crystal structure. Theemitter dip effect can be more efficiently prevented when the ratio ofarsenic to the impurity other than arsenic is selected to be equal to 340 100 or more preferably 8 2'4 100 in the atom ratio at the surface ofthe high concentration region. The term atom ratio" intends to mean aratio of atomic numbers per cubic centimeter.

The invention will be better understood from the following description,reference being made to the accompanying drawings, in which:

FIGS. 1A to ID are sectional views showing various steps ofmanufacturing an NPN-type planar transistor according to the presentinvention;

FIG. 2 is a diagram showing apparatus suitable for use in themanufacture of the transistor shown in FIGS.

1A to 1D; V

FIGS. 3A to 3E are sectional views showing various steps ofmanufacturing a modified PNP-type planar transistor;

FIGS. 4A to 4D show-sectional views of successive steps of manufacturinga diode according to the method of this invention;

FIGS. 5A to 5D are similar views showing successive steps ofmanufacturing a silicon controlled rectifier;

FIGS. 6A to 6D are photographs of semiconductor substrates of thisinvention and prior art taken by X-ray topography to show the presenceof lattice defects wherein FIGS. 6A and 6B show prior art devices, FIG.6C a device manufactured by a method similar to'this invention but theratio of arsenic to phosphorus is an outside of the scope of thisinvention and FIG. 6D shows the novel device.

FIGS. 7A and 7E are photographs taken by X-ray topography to show theeffect of the dislocation density of the substrate upon lattice defects;

FIG. 8A showsa graph to compare the noise figure of a novel NPN-typeplanar transistor with that of a prior similar transistor;

FIG. 8B shows a graph to show the relationship between the noise figureand the frequency of transistors utilizing different crystal surfaces.

FIGS. 9A to 9C compare various characteristics of a novel high frequencytransistor and of a prior art high frequency transistor wherein FIGS. 9Aand 9B show cut off frequency characteristics, and FIG. 9C the Vcharacteristics, and wherein in the cases of FIGS. 9B and 9C thesurfacesof the substrates are (111) faces;

FIG. 10 is a photograph of a novel high frequency transistor which showsthat no emitter dip effect is present;

FIG. 11 is a graph to show the relationship between the ratio of arsenicto phosphorus and the emitter dip effect;

ode; FIG. 14 compares the switching times of a novel.

FIG. 12 is a graph to show the relationship between the time of heattreatment and tha life times of a novel diode and of a conventionaldiode;

FIG. 13 is a connection diagram of a circuit employed to measure theswitching time of a switching diconcentration curves in the diffusedregions of a novel device and a prior device.

With reference first to FIGS. 1A to ID, the novel method ofmanufacturing an NPN-type planar transistor will be described hereunder.A silicon dioxide film 42 is applied onto one surface 41, preferably ofa (111) face, of an N-type conductivity silicon substrate 40 free fromdislocation as shown in FIG. 1A, and an opening is formed in the film 42by photoetching technique. A

P-type impurity is diffused into the substrate through this opening toform a P-type'conductivity region 43 thus forming a PN-junction betweenthe substrate 40 and the region 43, as shown in FIG..1B. In the planartransistor, the substrate 40 acts as acollector region andthe P-typeregion 43 as a base region. A silicon dioxidefilm is then applied ontothe surface 41 and an opening 44 is formed in this silicon dioxide filmat the center of the base region as shown in FIG. 1C. Then a gaseousmixture containing a mixture of silane (SiH and oxygen, and, at apredetermined ratio to be described later, a mixture of hydrogenphosphide (PH and hydrogen arsenide (AsH are applied on the exposedsurface of the substrate through opening 44 by using a suitableapparatus as diagrammatically shown in FIG. 2 to deposit a silicondioxide film doped with phosphor and arsenic on the exposed portion ofthe region 43, as shown in FIG. 1D.

The concentrations of respective impurities to be doped can be adjustedto any desired values by controlling the flow quantities of the hydrogenphosphide and hydrogen arsenide utilized to form the silicon dioxidefilm doped with these impurities. Accordingly, the flow quantities ofthe hydrogen phosphide and hydrogen arsenide are adjusted such that thequantity of arsenic in the doped region is larger than that of the otherimpurity (phosphorus in this case), in other words, in terms 4 of thenumbers of atoms, at a ratio of arsenic to'the other impurity of 3 40100, preferably 8 24 100.

Then the substrate is heat treated in a nitrogen atmosphere at atemperature of about l,lO0C for 4 hours to diffuse the impurities in thesilicon dioxide film into the P-type region 43 to form an N region 45acting as an emitter region. In the semiconductor device prepared asabove described, the ratio of the extent of the broadening of the basewidth caused by the emitter dip effect to the base width is less than0.2;1 which is of course negligebly small. When the N region is fonnedby diffusing an ordinary N-type impurity, for example, phosphorusoxychloride (POCI into a monocrystal- Iine substrate prepared by pull-upgrowing method as has been the common prior practice, and as the surfaceconcentration is increased to about 2.0 X atoms/cm, the dislocation andsegregation become significant. For this reason, it has been impossibleto increase the impurity concentration to the desired level. Whereas,when arsenic is incorporated into the doped region at a prescribed ratioaccording to the teaching of this invention, even when the surfaceconcentration is increased to 4.0 X 10 atoms/cm any lattice defect andsegregation can not be noted.

While in the foregoing description doped oxide method has been used todiffuse impurities to form the N region it is also possible to diffusethe impurities into the substrate by heating it together with sources ofimpurities in an opened or sealed tube. When using a sealed tube,sources of impurities may be suitable combinations of phosphoruspentaoxide, phosphor silicide, red phosphorus, silicon arsenide,arsenide and so forth. The type of the combination and the quantity ofthe source sealed in the tube are selected to produce above describedratio of the impurities in the diffused region. A suitable combinationof the source comprises red phosphorus and silicon arsenide. Further inthe above example, phosphorus was illustrated as the impurity other thanarsenide but it will be clear that impurities of the same conductivitytype, such as antimony, can also be used. Although doping only antimonyinto the substrate results in the dislocation, addition of arsenicprevents the generation of dislocation. In addition to the formation ofan N -region of high concentration of an NPN-type semiconductor device,the method of this invention is also applicable to form a P region ofhigh impurity concentration to manufacture a PNP-type semiconductordevice. In this case also the ratio of arsenic to the other impurity,e.g. phosphorus contained in the diffused region should be theprescribed ratio described above, more particularly in terms of thenumber of atoms the arsenic should amount to 3 40 percent, preferably 824 percent.

FIGS. 3A to 3E show successive steps of manufacturing a PNP-typesemiconductor device according to the method of this invention. On one'surface of a P -type silicon substrate 48 deeply doped with boron isformed a P-type region 49 by vapour phase growth technique as shown inFIG. 3A, and a silicon dioxide film is applied on the region 49. Anopening is formed in the silicon dioxide film. A gaseous mixture ofhydrogen phosphide (PH and hydrogen arsenide (AsH containing phosphorusand arsenic at a ratio of 100.: 8 24, in terms of the number of atoms,is used to form a doped oxide layer 50 on the silicon dioxide film andon the area of the region 49 exposed in the opening whereby to diffusephosphorus and arsenic in the P-type region, thus forming an N-typeregion 51 acting as a base region as shown in FIG. 3C. Then, a 50 lgaseous mixture of boron hydride (B l-l and hydrogen arsenide (AsH isadmitted into an opened tube diffusing apparatus to form an oxide film52 doped with boron and arsenic on the silicon dioxide film and theN-type region 51, as shown in FIG. 3D. The assembly is then heated for1.5 hours at a temperature of about l,l00C to diffuse boron and arsenicinto the N-type region 51 to form a P -type region 53 acting as anemitter region, as shown in FIG. 35. Under these conditions, it ispossible. to form an emitter region having a surface concentration of 3X 10* atoms/cm and a thickness of 3 microns. The use of the oxide filmdoped with arsenic causes the generation of little stress in the film.

FIGS. 4A to 4D show successive steps of manufacturing a diode accordingto the method of this invention. Thus, arsenic and at least one N-typeconductivity impurity other than arsenic are diffused into the oppositesurfaces of an N-type conductivity silicon substrate 54 to form N -typeconductivity regions 55 on both sides thereof and then one of the N-type regions is removed as shown in FIG. 4A. In this case, the quantityof the arsenic diffused in the N -type conductivity region is determinedwith respect to the quantity of the N-type conductivity impurity otherthan arsenic to have a value within a range of 8 24 percent in terms ofthe number of atoms. Then all surfaces of the substrate are covered witha silicon dioxide film 56 and at least one P-type conductivity impurityand arsenic are diffused into the substrate 54 at a definite ratiothrough an opening 57 formed in the silicon dioxide film to form aPf-type conductivity region 58 in the substrate 54 as shown in FIG. 4C.Again the quantity of the arsenic diffused in the P -type conductivityregion is determined with respect to the quantity of the P-t'ypeconductivity impurity to have avalue within a range of 8 24 percent interms of the number of atoms. Then the silicon dioxide film 56 isremoved and an anode electrode 60 and a cathode electrode 59 are securedto the P region 58 and the N region 55, respectively to complete adiode, as shown in FIG. 4D. It was possible to increase the impurityconcentrations in the diffused regions fabricated in the manner as abovedescribed to a high value of 7.5 X 10 atoms/cm, for example, and thefact that there is no lattice defect in the diffused regions wasconfirmed by X-ray photography.

FIGS. 5A to 5D illustrate successive steps of manufacturing a siliconcontrolled rectifier. Again, arsenic and at least one P-typeconductivity impurity are diffused into the opposite surfaces of anN-type conductivity silicon substrate 61 at a definite ratio to form P-type conductivity regions 62 and 63 on the opposite sides of thesubstrate. The quantity of the arsenic diffused in the P-typeconductivity regions is determined with respect to the quantity of. theP-type conductivity impurity to have a value within a preferred range of8 24 percent, in terms of the number of atoms. Then, the entire surfaceof the substrate is covered with a silicon dioxide film 64 as shown inFIG. 5A and an opening 65 is formed through the portion of the silicondioxide film 64 overlying one of the P-type conductivity regions 63 asshown in FIG. 5B. Arsenic and at least one N-type conductivity impurityother than arsenic are diffused through opening 65 at a definite ratioto form an N -type conductivity region 66 in one of the P-typeconductivity regions 63, as shown in FIG. 5C. The quantity of thearsenic diffused in the N-type conductivity region 66 is determined withrespect to the quantity of the N-type conductivity impurity to have avalue within a preferred range of 8 24 percent, in terms of the numberof atoms. After removal of the silicon dioxide film 64, metal films arevapour deposited on the N type region 66, the portion of the P-typeregion 63 adjacent thereto and the other P-type region 62 respectivelyto form a cathode electrode 67, a gate electrode 68 and an anodeelectrode 69 whereby to complete a silicon controlled rectifier, asshown in FIG. 5D.

While semiconductor devices illustrated hereinabove utilize siliconsubstrates formed by a conventional method, a floating zone process, forexample, the merit of this invention can be enhanced when use is made ofthe so-called dislocation free silicon substrate. The term dislocationfree silicon used herein means a silicon body havinga dislocationdensity of less than 1,000 FIGS. 6A to 6D show photographs of thesubstrate cm' such a silicon body may be produced by a surfaces diffusedwith impurities according to this inmethod disclosed in Japanese patentpublication No. vention and to a prior method and taken by X-rayphol8,402 of 1965 relating to an improvement of the floattography. Thesubstrates utilized comprised N-type ing zone method or the pedestalpulling method deconductivity silicon crystals having a dislocationdenscribed in Applied Physics, 31, 736 (1930). According to y of .000 o6.000 and a specific resistivity of 1 to the latter method a siliconbody is mounted on a ped- Z OhmS-Cm and their 1l l) faces were utilizedas the estal provided with slits for preventing flow of high fremainsurfaces. FIG. 6A shows a photograph of. a subquency current and thesilicon body is melted in an strate diffused with only arsenic by theprior method inert atmosphere in vacuum by means of high freandcontaining many defects which are shown as black quency inductionheating. Then an extremely fine seed spots and stripes. FIG. 6B shows aphotograph of a subcrystal is dipped in the molten silicon and the seedcrysstrate diffused with only phosphorus by the prior tal is pulledupwardly while being rotated thus growing method also containing a greatmany defects. FIG. 6C pure crystal of silicon. shows a photograph of themain surface of a substrate Not only silicon but also the othersemiconductors doped with both arsenic and phosphorus like the semisuchas germanium can also be used in he form of i conductor device of thisinvention but the ratio of arselocation free crystals. nic andphosphorus is 150 100, in terms of the number We have confirmed byexperiments that defects of of atoms which is outside the scope of thisinvention. the crystals such as lattice defects and segregations Thesubstrate contains many defects. FIG. 6D shows a caused bydiffusingimpurities into the substrate are photograph of a substrate doped witharsenic phosphoalso influenced by the orientations of the crystals on msat a rati f 3 t 6 100 i t m f the number f the surface of the substrate.We have also found that at ms, I this c e, the number of def ts isextremely use of the (111) face as the main surface or the surface all,to be diffused with impurities minimizes the creation of FIGS. 7A to 7Cshow photographs of silicon subsuch defects. For this reason, in thebove cri strates of different dislocation densities. These photoexamplesthe faces were ed s he main SUP graphs show the relationship between thedislocation faces of the substrates. density and the creation of thedefects. FIGS. 7A to 7C Table -l below shows measured a ue of the defectshow photographs of substrates having dislocation dendensity of varioussemiconductor devices prepared acid f more th 1,000 al to 2000 5000cording to the method of this invention and utilizing nd more th 10,000a d diff d with different crystal faces as'the main surfaces of thesubphosphorus i h (111) faces h f to id a strates. surface density of 4X 10 cm each. These figures TABLE I show that the number of defectsformed increases in i I proportion to thedislocation density of thesubstrates. ge fifii gfj FIGS. 7D and 7E show photographs of siliconsubilllgni /l g :0 Good 40 strates having dislocation densities of morethan 2,000 2 ,3 X 21 numerous bad cm' and less than 1,000 cmrespectively and are dif- (ll0) i.-2 x 10:: nume fused with arsenic andphosphorus at a ratio of 8 24 i :8 fijgg ggg 100, in terms of the numberof atoms, to a surface (8] l) 1.2 x i0 numerous bad density of 7 X 10cm. As can be clearly noted from X bad FIGS. 7A to 7B, the number ofdefects formed de- (2I0) l.2 X 10 many bad I (322) 1.3 x i0" numerousbad creases with the dislocation density of the substrate and 320 |.2 X10 V n o 7 I bad becomes lesser when both phosphorus and arsenic are Inthe above table, dislocation free silicon substrates e at a definite a oan e either One O ese were used as the semiconductor substrates and theimmp r is used alonepurities were diffused by utilizing silicon dioxidefilms when arsenic and at least one p y Other doped with phosphorus andarsenic at a predeter i d senic are diffused together in the substratein accorratio. dance with this invention at a ratio such that the num-According to a prior method defects are formed ber of atoms of arsenicis lesser than that of the other when the surface concentration in thediffused region impurity it is possible to greatly decrease the numberin the substrates exceeds 8 X 10 atoms/cm but in the of lattice defectsformed as shown in table 2 below.

We TABLE 2 Fmm mi m --a---- Ratio of phosphorus to arsenic SurfaceThick- Surfaca concentration (in terms of density ness of (atom/cm!)arsenic the number (atoms/ Curvature diflusad phosphorus of atoms) Typeof substrate cm!) (111:) layer (It) o aoxio 0:100 SubstrateC-Z 2. 0x10 01.22 7.2X1M/0AX1M :5.56 --do 7. sxro' 1 same- 4.1 aaxlo o 100:0 do 3.8X10" 1 92x10- 4.0 amm /0.3mm- 100:4.43 Dislocation tree substrate" 7.0x10 -a.44x1o a. s 4.o 1o o.-.....- 100:0 do 4.0XIO" 1.0sx10-= 4.0

semiconductor devices prepared by the method of this invention andutilizing the (111) faces as the main surfaces the defect density can bereduced to substantially zero as shown in table 1.

,C-Z substrate means a silicon substrate prepared by Czochralski meltingzone method which generally has dislocation density.

a bi h lhe dislocation free substrate means a silicon substrate having adislocation density of less than 1000 and prepared by the pedestalpulling met This table shows that, in substrates doped with bothphosphor and arsenic at a ratio of 100 4.48 or 100 5.56 it is possibleto form regions of higher impurity concentrations than when onlyphosphorus or arsenic is diffused and that the curvature of thesubstrate is smaller or the substrate does not warp appreciably whencompared with the case in which only phosphorus is doped.

While it has been known in the art to simultaneously diffuse an impurityhaving larger lattice constant than silicon, for example, tin(Sn) and animpurity having a smaller lattice constant than silicon, such asphosphorus (P) or boron (B) for the purpose of decreasing diffusionstrain, it should be noted that the invention is quite different fromsuch a method. When selectively diffusing above described combination oftin and phosphorus or a combination of tin and boron, the presence oftin interferes with the selective diffusion of the silicon dioxide filmthus resulting in the diffusion of boron or phosphorus through thesilicon dioxide film. It is also difficult to simultaneously diffuse tinand phosphorus, boron and phosphorus or tin and boron.

In contrast, the method of utilizing arsenic, the diffusion proceedsreadily. Especially, when using a combination of phosphorus and arsenic,since these impurities are both N-type, it is possible to increase thesurface concentration than in the case wherein only phosphorus isdiffused.

Following examples are given by way of illustration but not limitation.

l. NPN-Planer Type Semiconductor Device Boron nitride (BN) was diffusedinto one surface of a dislocation free N-type conductivity siliconsubstrate having a specific resistivity of 4 ohm-cm to form a baseregion. The emitter region was formed by diffusing an impurity mixtureof phosphorus and arsenic to a surface concentration of 4 X IO /Cm bymeans of the doped oxide coating method to complete a semiconductordevice for audio frequency use. The noise figure of this semiconductordevice was compared with that of a similar semiconductor devicecomprising a silicon substrate prepared by the conventional pull-upmethod and diffused with impurities in the same manner. FIG. 8A showsthis comparison wherein the solid lines show the noise figure of thedevice whereas the dotted lines that of the conventional device. Asshown by the solid lines the semiconductor device has an extremely lownoise figure of 1 dB at a frequency of 120 Hz and at a rating of 6 V, 1mA and 500 ohms, for example. FIG. 8B shows noise figures of NPN-typetransistors utilizing substrates having main surfaces of the crystalfaces of the orientations of (111) face (curve A), (100) face (curve B)and (311) face (curve C) respectively.

2. Semiconductor Device for High Frequency Use A mixture of phosphorusand arsenic containing the latter at a ratio of 8 24 percent in terms ofthe number of atoms was doped into a main surface of a dislocation andoxygen free N-type conductivity silicon substrate having a specificresistivity of 4 ohm-cm to form an emitter region of a surfaceconcentration of 4 X l/cm by means of the above described doped oxidecoating method to obtain a transistor for high frequency use. A similartransistor was formed by using a silicon substrate prepared by theconventional pull-up method but diffused with impurities in the samemanner just described. As shown by the solid lines in FIG. 9A, theaverage value of the cut-off frequency of the semiconductor devices wasabout 1,500 MHz, whereas that of the conventional semiconductor devicewas about 700 MHz as shown by the dotted lines in FIG. 9A. In highfrequency semiconductor devices, although it is necessary to decreasethe base width in order to improve the high frequency characteristics,this tends to decrease the emitter-collector breakdown voltage VHowever, in the semiconductor devices of this invention utilizingdislocation free substrates such decrease in V is not noted and yet V ishigher by about 15 volts than conventional overlay transistors.

While in the above described examples dislocation free monocrystallinesubstrates were used, when a (111) face was used, results as shown inFIGS. 98 and 9C were obtained. As shown by the dotted line curve shownin FIG. 98, according to the prior method, it was impossible to obtainsemiconductor devices having cutoff frequencies of more than 900 MHz,but according to this invention it is possible to produce semiconductordevices having higher cut-off frequencies of 900 to 1,000 MHz, as shownby the solid lines. FIG. 9C compares the distribution of values of V (adc voltage between collector and emitter electrodes when the baseelectrode is opened) of the semiconductor devices utilizing the (111)face and are fabricated by the method of this invention (solid lines)and of the semiconductor devices prepared by the conventional method(dotted lines). FIG. 9C shows that the semiconductor devices have largerand more stable V As can be noted from the photograph shown in FIG. 10it is possible to readily provide the desired base width because of theabsence of the emitter dip effect, thus improving the high frequencycharacteristics.

According to the method of this invention, there is no tendency ofincreasing the base width caused by the emitter dip effect as in theconventional semiconductor devices. FIG. 11 shows a diagram to explainthe relationship between the ratio of base width to the emitter dip andthe ratio of arsenic to phosphorus. FIG. 11 clearly shows that a rangefrom 8 to 24 percent of As/p provides the minimum value of less than0.15, of the ratio of the base width to the emitter dip and range from 3to 40 percent of As/p causes a relatively smaller emitter dip effect.This preferred range was confirmed by determining a range in whichcreation of the defects (which are believed to be caused by theprecipitation of phosphorus) is remarkably reduced, by means of X-raytopography. The exact theory for this is not yet clearly understood, andit is considered that the precipitation of phosphorus is prevented bythe presence of arsenic. For this reason, base widths exactly the sameas the designed values, for example one micron or less, can be readilyassured, thus producing at high yields high frequency semiconductordevices having cutoff frequencies of more than 1,000 MHz.

When fabricating a semiconductor device, or an integrated circuit devicehaving a plurality of mutually insulated circuit elements adjacent onemain surface of a semiconductor substrate, it is possible to fonnjunction regions of small widths, because, in the steps of formingdiffused layers of the PN junctions of the circuit elements, the N or Pregions can be formed to have high concentrations without forminglattice defects and because the width of the regions adjacent the N or Pregions is not broadened by the emitter dip effect during the formationof the high concentration regions. Thus, similar to the above describedNPN-type semiconductor devices and diodes it becomes possible to obtainat high yields integrated circuits having circuit elements of improvednoise and 'high frequency characteristics.

3. Diode When forming a diffused region of a high impurity concentrationin a dislocation free semiconductor substrate for the purpose ofobtaining a diode, since, acoording to this invention, an impurityincorporated with arsenic is diffused no defect due to diffusion strainis formed in the region. Accordingly, the impurities will notprecipitate in the defects but maintained in a supersaturated state,thus manifesting electrical activity. Thus, for example, even when alarge mesa type diode is heat treated at a temperature of 100 to 300Cover a long time, the life time is not affected. FIG. 12 is a graph tocompare the relationship between the life time and the period of heattreatment of the diode prepared according to the methodof this invention(solid line curve A) and of the diode of the prior art (dotted linecurve B). The same advantage can also be obtained by a diode utilizingthe 111) face as the main surface. In a switching diode, since there isno lattice defect in the layer containing impurities at a highconcentration, the

segregation of gold will not occur. For this reason, it is possible toreadily control the concentration of gold near the PN-junction thusdecreasing deviations of the switching time from the reference value.Generally, the measurement of the switching time Trr is made by using acircuit as shown in FIG. 13. Typical results of the measurement areshown in FIG. 14 as shown by the dotted curve B, prior art switchingdiodes show an average switching time of 2.0 ,u sec and maximumdeviation of l ,u. sec whereas those of this invention show an averageof 2.0 u sec and maximum deviation of only 0.03 ,u. see as shown bysolid line curve A which shows that the switching diodes have uniformcharacteristics.

4. Silicon Controlled Rectifiers FIGS. 15A and 158 show graphs tocompare the relationship between the forward voltage drop and the heattreatment time of the silicon controlled diodes predevice for highfrequency application. Further, in accordance with this invention it ispossible to decrease the deviation in the switching time of a switchingdiode and to decrease the forward voltage drop of a silicon cotrolledrectifier due to heat treatment. The novel method can'also be applied tointegrated circuits with equal advantage.

pared according to this invention (curves A) and of those of the priorart (curves B). FIG. 15A shows the characteristics of the siliconcontrolled rectifiers utilizing dislocation free substrates whereas FIG.15B those paring curves A and B it will be clear that the forwardvoltage drop of the silicon controlled rectifiers is lower than that ofthe prior art which is the desirable characteristic.

Curves shown in FIG. 16 show impurity distributions in a region formedby diffusing a lesser quantity of arsenic than phosphorus, in a-regioncontaining a larger of the base width is effectively prevented, it ispossible to increase the cut off frequency of the semiconductor What weclaim is:

l. A semiconductor device having a highly doped, defect free regioncomprising:

a. a silicon semiconductor substrate; and

b. a highly doped region formed simultaneously in one surface of saidsubstrate including at least one first impurity selected from the groupconsisting of phosphorus and boron, said highly doped region furtherincluding a second impurity of arsenic to compensate for a dislocationof the highly doped region when said first impurity is doped in thesubstrate, the concentration of the second impurity being 3 40 percentof that of the first impurity.

2. semiconductor substrate is free from dislocation.

3. A semiconductor device of claim 1, wherein said one surface of saidsubstrate is (111) face.

4. A semiconductor device of claim 1, wherein said silicon semiconductorsubstrate has three alternatively different conductivity type regions.

5 A semiconductor device having a highly doped,

defect free region comprising:

a. a silicon semiconductor substrate having one conductivity type; and

b. a highly doped region forming a P-N junction in said substrate, saidregion having opposite conductivity type to that of saidsubstrate andincluding at least one first impurity selected from the group consistingof phosphorus and boron, said region further including a second impurityof arsenic to compensate for a dislocation of the highly doped regionwhen said first impurity is doped in the substrate, the concentration ofthe second impurity being 3-40 percent of that of the first impurity,and said first and second impurities being included in said regionsimultaneously. V

6. A semiconductor device having a highly dopeddefssttfrss.rssisnssmsrisinsi a. an N type'silicon semiconductorsubstrate having a highly doped N type region in one surface of saidsubstrate, said N type region including arsenic and phosphorus and saidarsenic and phosphorus being included insaid region simultaneously; and

b. a highly doped P type region in an opposite surface of saidsubstrate, said P region including arsenic and boron and saidarsenic andboron being included in said region simultaneously, said arsenic in N*and P type regions compensating for a dislocation of both regions whensaid phosphorus and boron are doped in the substrate, the concentrationof said arsenic of N* and P type regions both being 3-40 percent of thatof phosphorus and boron in and P type regions, respectively.

7. A semiconductor deviceTTzi viiig ii iniaabd,

defect free region comprising:

a. a silicon semiconductor substrate forming a collector region;

b. a base region forming a P.-N junction with said collector region inone surface of said substrate; and

A semiconductor of claim 1, wherein said silicon c. a highly dopedemitter region forming a P-N juncdefect free region comprising:

a. a silicon semiconductor substrate; b. an epitaxial growth region onsaid substrate; and

defect free region comprising:

a. a silicon semiconductor substrate having one conductivity type;

b. an epitaxial growth region on said substrate having the sameconductivity type as said substrate; and

c. a highly doped region forming a P-N junction in said epitaxial growthregion, said region having opposite conductivity type to that of saidsubstrate and including at least one first impurity selected from thegroup consisting of phosphorus and boron, said region further includinga second impurity of arsenic to compensate for a dislocation of thehighly doped region when said first impurity is doped in the substrate,the concentration of the second impurity being 340 percent of that ofthe first impurity, and said first and second impurities being includedin said region simultaneously.

10. A semiconductor device having a highly doped,

defect free region comprising:

a. a silicon semiconductor substrate;

b. an epitaxial growth region on said substrate, said region and saidsubstrate forming a collector region;

c. a base region forming a P-N junction with said collector region insaid epitaxial growth region; and d. a highly doped emitter regionforming a P-N junction in said base region, said emitter regionincluding at least one first impurity selected from the group consistingof phosphorus and boron, said emitter region further including a secondimpurity of arsenic to compensate for a dislocation of the emitterregion when said first impurity is doped in the substrate, theconcentration of the second impurity being 3-40 percent of that of thefirst impurity, and said first and second impurities being included insaid region simultaneously.

2. A semiconductor of claim 1, wherein said silicon semiconductor substrate is free from dislocation.
 3. A semiconductor device of claim 1, wherein said one surface of said substrate is (111) face.
 4. A semiconductor device of claim 1, wherein said silicon semiconductor substrate has three alternatively different conductivity type regions.
 5. A semiconductor device having a highly doped, defect free region comprising: a. a silicon semiconductor substrate having one conductivity type; and b. a highly doped region forming a P-N junction in said substrate, said region having opposite conductivity type to that of said substrate and including at least one first impurity selected from the group consisting of phosphorus and boron, said region further including a second impurity of arsenic to compensate for a dislocation of the highly doped region when said first impurity is doped in the substrate, the concentration of the second impurity being 3-40 percent of that of the first impurity, and said first and second impurities being included in said region simultaneously.
 6. A semiconductor device having a highly doped defect, free region comprising: a. an N type silicon semiconductor substrate having a highly doped N type region in one surface of said substrate, said N type region including arsenic and phosphorus and said arsenic and phosphorus being included in said region simultaneously; and b. a highly doped P type region in an opposite surface of said substrate, said P region including arsenic and boron and said arsenic and boron being included in said region simultaneously, said arsenic in N and P type regions compensating for a dislocation of both regions when said phosphorus and boron are doped in the substrate, the concentration of said arsenic of N and P type regions both being 3-40 percent of that of phosphorus and boron in N and P type regions, respectively.
 7. A semiconductor device having a highly doped, defect free region comprising: a. a silicon semiconductor substrate forming a collector region; b. a base region forming a P-N junction with said collector region in one surface of said substrate; and c. a highly doped emitter region forming a P-N junction in said base region, said emitter region including at least one first impurity selected from the group consisting of phosphorus and boron, said emitter region further including a second impurity of arsenic to compensate for a dislocation of the emitter region when said first impurity is doped in the substrate, the concentration of the second impurity of arsenic being 3-40 percent of that of the first impurity, and said frist and second impurities being included in said region simultaneously.
 8. A semiconductor device having a highly doped, defect free region comprising: a. a silicon semiconductor substrate; b. an epitaxial growth region on said substrate; and c. a highly doped region formed simultaneously in said epitaxial region including at least one first impurity selected from the group consisting of phosphorus and boron, said highly doped region further including a second impurity of arsenic to compensate for a dislocation of the highly doped region when said first impurity is doped in the substrate, the concentration of the second impurity being 3-40 percent to that of the first impurity.
 9. A semiconductor device having a highly doped, defect free region comprising: a. a silicon semiconductor substrate having one conductivity type; b. an epitaxial growth region on said substrate having the same conductivity type as said substrate; and c. a highly doped region forming a P-N junction in said epitaxial growth region, said region having opposite conductivity type to that of said substrate and including at least one first impurity selected from the group consisting of phosphorus and boron, said region further including a second impurity of arsenic to compensate for a dislocation of the highly doped region when said first impurity is doped in the substrate, the concentration of the second impurity being 3-40 percent of that of the first impurity, and said first and second impurities being included in said region simultaneously.
 10. A semiconductor device having a highly doped, defect free region comprising: a. a silicon semiconductor substrate; b. an epitaxial growth region on said substrate, said region and said substrate forming a collector region; c. a base region forming a P-N junction with said collector region in said epitaxial growth region; and d. a highly doped emitter region forming a P-N junction in said base region, said emitter region including at least one first impurity selected from the group consisting of phosphorus and boron, said emitter region further including a second impurity of arsenic to compensate for a dislocation of the emitter region when said first impurity is doped in the substrate, the concentration of the second impurity being 3-40 percent of that of the first impurity, and said first and second impurities being included in said region simultaneously. 